In the world of programmable logic development tools, the latest may not be the greatest!!!...Do you agree with me? Recently I went through a horrible experience working with Lattice CPLDs & their development tool. A couple of years back, some old CPLD devices were replaced with new CPLDs and the old ABEL codes were re-synthesized using ispLEVER software from Lattice. The re-compiled codes worked fine with the new devices. The designers did not bother to preserve the version of the ispLEVER software tool they used to compile the ABEL codes, since they were only concerned about archiving the source codes and other inout information to the tool.
In the recent past, there was a need to make a minor modification to some of these CPLD codes. By this time, we no more had the version of the ispLEVER software that was used to compile the ABEL codes a couple of years back. I downloaded the latest ispLEVER Classic software from the Lattice website and compiled the same ABEL code with out any changes in it. I downloaded the .jed file to the respective CPLD and to my surprise, the board did not work.
After a lots of hard work, debugging with a logic analyser, I found the root of the problem lied in the new version of the compiler, which mis-interpreted some portion of the ABEL code related to the bi-directional signals. After that, it took a while to fix this by adding some extra pins, board revision etc.
This incident taught me a lesson. When ever I finish a design, I would keep the version of the development tool used for development, archived along with the tool. This would consume more storage space, but would save some time spent in re-work. Again, in a big organization, it may not be always possible to archive each version of tool used for designs. In that case the designer has to be foresighted to be able to write a device architecture independent & synthesis tool independent code using popular HDLs such as VHDL/Verilog or other high level languages such as System C.
In the recent past, there was a need to make a minor modification to some of these CPLD codes. By this time, we no more had the version of the ispLEVER software that was used to compile the ABEL codes a couple of years back. I downloaded the latest ispLEVER Classic software from the Lattice website and compiled the same ABEL code with out any changes in it. I downloaded the .jed file to the respective CPLD and to my surprise, the board did not work.
After a lots of hard work, debugging with a logic analyser, I found the root of the problem lied in the new version of the compiler, which mis-interpreted some portion of the ABEL code related to the bi-directional signals. After that, it took a while to fix this by adding some extra pins, board revision etc.
This incident taught me a lesson. When ever I finish a design, I would keep the version of the development tool used for development, archived along with the tool. This would consume more storage space, but would save some time spent in re-work. Again, in a big organization, it may not be always possible to archive each version of tool used for designs. In that case the designer has to be foresighted to be able to write a device architecture independent & synthesis tool independent code using popular HDLs such as VHDL/Verilog or other high level languages such as System C.
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