HIGH VOLTAGE SURGE:
In the previous parts the nature of ESD, EFT noise was discussed along with a brief illustration of the design techniques to make the electronics system more immune to the noise. I wish to present a much more detailed list of the circuit design and board layout recommendations and best practices later once we could touch upon all the types of the noises mentioned by the IEC/EN standards specifying noise immunity testing. In the subsequent few parts the threat of voltage surge and techniques will be discussed.
Before we go ahead to the next topic, I would like to put some food for thought through here. The question is related to EFT testing of Ethernet port. Have you ever seen shielded cable failing during EFT testing at a voltage level lower than the level at which the test passes with an unshielded cable? Can this happen? Please feel free to let your thought captured in the comments.
OK, coming back to the Voltage Surge topic, first we need to understand the nature of the surge. I consider voltage surge a bit different from the other types of electromagnetic disturbances such as ESD, EFT we have seen so far. I would not classify voltage surge as noise similar to ESD, EFT, RF as the frequency of surge is much lower compared to that of ESD, EFT etc. But the energy content in a surge pulse is much higher compared to ESD, EFT for a given voltage level.
In the standard document IEC61000-4-5, the surge waveforms of open-circuit voltage and short circuit current are specified for a couple of different (front time/time to half-value) combinations, which closely simulate the real world surge waveforms, caused by overvoltage conditions from switching and lightning transients. If you are going for surge testing, you will need to go through the applicable standard documents to gather detailed information on the same. To present a basic idea here, I have illustrated the nature of the open-circuit voltage waveform of (1.2/50 us) surge voltage in the picture below:
In general, for a IO line or communication line, the peak value of the surge voltage applied during testing is 1KV. Compared to 1KV EFT pulses, we could easily make out that 1KV surge pulse would impose much more energy to the device under test.
In the next part we will see how the surge voltage is applied to the device under test and how we could handle that in the circuit design.
In the previous parts the nature of ESD, EFT noise was discussed along with a brief illustration of the design techniques to make the electronics system more immune to the noise. I wish to present a much more detailed list of the circuit design and board layout recommendations and best practices later once we could touch upon all the types of the noises mentioned by the IEC/EN standards specifying noise immunity testing. In the subsequent few parts the threat of voltage surge and techniques will be discussed.
Before we go ahead to the next topic, I would like to put some food for thought through here. The question is related to EFT testing of Ethernet port. Have you ever seen shielded cable failing during EFT testing at a voltage level lower than the level at which the test passes with an unshielded cable? Can this happen? Please feel free to let your thought captured in the comments.
OK, coming back to the Voltage Surge topic, first we need to understand the nature of the surge. I consider voltage surge a bit different from the other types of electromagnetic disturbances such as ESD, EFT we have seen so far. I would not classify voltage surge as noise similar to ESD, EFT, RF as the frequency of surge is much lower compared to that of ESD, EFT etc. But the energy content in a surge pulse is much higher compared to ESD, EFT for a given voltage level.
In the standard document IEC61000-4-5, the surge waveforms of open-circuit voltage and short circuit current are specified for a couple of different (front time/time to half-value) combinations, which closely simulate the real world surge waveforms, caused by overvoltage conditions from switching and lightning transients. If you are going for surge testing, you will need to go through the applicable standard documents to gather detailed information on the same. To present a basic idea here, I have illustrated the nature of the open-circuit voltage waveform of (1.2/50 us) surge voltage in the picture below:
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| Figure 1: Open-circuit voltage waveform (1.2/50 us) at the output of surge generator with no CDN connected |
In Figure 1 above, T1 is the "Front Time", which is defined in the standard as a virtual parameter 1.67 times T (time taken by the impulse voltage to rise from 30% to 90% of its peak value).
T2 is the "time to half-value", which is the time interval between the virtual origin VO and the time instant when the impulse voltage falls to 50% of its peak value.
For the above voltage waveform, as specified in IEC61000-4-5 standard,
T1 = 1.67 x T = 1.2 us +/- 30%
T2 = 50 us +/- 20%
In the next part we will see how the surge voltage is applied to the device under test and how we could handle that in the circuit design.
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