Quick Fundas: BJT# 1

What happens to VOUT when the source V1 is varied from +12V to +20V? Also, what will be the nature of variation of the current through R1 during this time? How could this circuit be useful? The Zener diode D2 has a breakdown voltage of 10V.

Figure 1: PNP Transistor Circuit

Hints: The circuit drives nearly constant current through R1 even though voltage V1 varies from +12V to +20V. Due to constant current through R1, voltage VOUT remains almost constant with respect to the positive rail (VOUT gets clamped with respect to positive rail of V1 irrespective of the variation of V1).

Using NPN transistors, the circuit below would provide nearly constant voltage ~9.6V at VOUT with respect to ground even if the input voltage varies between 12V and 30V.

Figure#2: NPN Transistor Clamp Circuit

One application of this circuit is to use this circuit to clamp the voltage of the gate drive of the MOSFET when the voltage used for the gate drive could vary over a wide range.   

Quick Fundas: Op-amp# 5

A slight improvement to the circuit described previously in "Quick Fundas: Op-amp# 4" is to add a capacitor C1 in parallel with R3. The capacitor C1 and R3 should be chosen appropriately to filter out over-voltage glitches that mostly occurs during power-up.

Figure 1: Improved Over-voltage detection circuit with latch

Quick Fundas: Op-amp# 4

Can we use the circuit similar to what is referred in "Quick Fundas: Op-amp# 3" to build an over-voltage monitoring circuit, which shall latch an over-voltage condition, i.e. even if the over-voltage occurs temporarily, the circuit should be able to continue driving the over-voltage shutdown trigger? The Op-amp should work with single +12V supply. The circuit should have provisions to adjust the threshold voltage levels for over-voltage detection (the voltage monitored could be different than the supply voltage to the Op-amp).

Ans:
There could be different ways to do it. The circuit below also should work. The circuit monitors the voltage "VMON" and drives "VOUT" to its positive rail when VMON goes above ~6.8V. The output VOUT gets latched even when VMON comes back to its nominal value. The latching feature is sometimes required for the user to understand an over-voltage condition has occurred. Changing R2, R3, R1 etc., the voltage threshold level could be adjusted. 

Figure 1: Over-voltage latch circuit diagram

The simulated waveforms are shown below:

Figure 2: Simulated waveform

     

Quick Fundas: Op-amp# 3

Another nice application of positive feedback to op-amp:

Can you think of building a SET-RESET latch circuit, which could be built using an op-amp, resistors and diodes? Assume that the op-amp is a rail-to-rail op-amp. 

Hints: You might need to use diodes in feedback and you might need to use positive feedback. 

If you are too much exhausted thinking, take look at the link below:

http://www.edn.com/design/other/4373768/Use-an-op-amp-as-a-set-reset-flip-flop

Quick Fundas: Op-amp#2

Another basic question that is sometimes asked to the fresh engineers during interviews:

When a positive feedback is added to an op-amp configured as comparably as shown in the picture below, how does the circuit behave? What is this circuit popularly known as? Could you please draw the transfer characteristics for the same?

In the picture below, VREF is a reference voltage, VIN is the voltage input and VOUT is the output of the Op-Amp.

Ans:

Without the positive feedback added using R2 above, the circuit behaves as a comparator. In that condition, considering the Op-Amp an ideal Op-Amp, when VIN rises just greater than VREF, the output of Op-Amp is driven to positive saturation voltage level VH. Again when VIN falls just lower than VREF, then VOUT goes to negative saturation voltage level VL. With R2 added as positive feedback, the circuit behaves as a Schmitt triggered comparator /buffer. With R2 in the circuit, when VIN rises more than VTH (see equation below) then VOUT is driven to positive saturation voltage level VH. Again when VIN falls lower than VTL (see equation below) then VOUT goes to negative saturation voltage level VL. Please note that VTH > VTL and the voltage difference (VTH - VTL) is the hysteresis band. The transfer characteristics is shown below:

VTH = VS - (R1/R2)*VL; 

VTL = VS - (R1/R2)*VH;

Where, VS = (1 + R1/R2)*VREF. 

    

Quick Fundas: Op-amp#1

There is a question that is commonly asked to the engineers appearing for the interviews at the initial stage of their career:

What are the few important parameters of an Op-amp? How do those parameters for a real-life Op-amp compare with those of a theoretically ideal Op-amp?

The table below shows some of the most important parameters of an ideal Op-amp vs. the same for a general purpose real-life Op-amp:

   

My Experience With "Noise": Part IVa

HIGH VOLTAGE SURGE:

In the previous parts the nature of ESD, EFT noise was discussed along with a brief illustration of the design techniques to make the electronics system more immune to the noise. I wish to present a much more detailed list of the circuit design and board layout recommendations and best practices later once we could touch upon all the types of the noises mentioned by the IEC/EN standards specifying noise immunity testing. In the subsequent few parts the threat of voltage surge and techniques will be discussed.

Before we go ahead to the next topic, I would like to put some food for thought through here. The question is related to EFT testing of Ethernet port. Have you ever seen shielded cable failing during EFT testing at a voltage level lower than the level at which the test passes with an unshielded cable? Can this happen? Please feel free to let your thought captured in the comments.

OK, coming back to the Voltage Surge topic, first we need to understand the nature of the surge. I consider voltage surge a bit different from the other types of electromagnetic disturbances such as ESD, EFT we have seen so far. I would not classify voltage surge as noise similar to ESD, EFT, RF as the frequency of surge is much lower compared to that of ESD, EFT etc. But the energy content in a surge pulse is much higher compared to ESD, EFT for a given voltage level. 

In the standard document IEC61000-4-5, the surge waveforms of open-circuit voltage and short circuit current are specified for a couple of different (front time/time to half-value) combinations, which closely simulate the real world surge waveforms, caused by overvoltage conditions from switching and lightning transients. If you are going for surge testing, you will need to go through the applicable standard documents to gather detailed information on the same. To present a basic idea here, I have illustrated the nature of the open-circuit voltage waveform of (1.2/50 us) surge voltage in the picture below:

Figure 1: Open-circuit voltage waveform (1.2/50 us) at the output of surge generator with no CDN connected

In Figure 1 above, T1 is the "Front Time", which is defined in the standard as a virtual parameter 1.67 times T (time taken by the impulse voltage to rise from 30% to 90% of its peak value).

T2 is the "time to half-value", which is the time interval between the virtual origin VO and the time instant when the impulse voltage falls to 50% of  its peak value.         

For the above voltage waveform, as specified in IEC61000-4-5 standard, 

T1 = 1.67 x T = 1.2 us +/- 30%

T2 = 50 us +/- 20%

In general, for a IO line or communication line, the peak value of the surge voltage applied during testing is 1KV. Compared to 1KV EFT pulses, we could easily make out that 1KV surge pulse would impose much more energy to the device under test.

In the next part we will see how the surge voltage is applied to the device under test and how we could handle that in the circuit design.