Quick Fundas: Op-amp# 6 Contd...

In the Op-amp circuit application example "Quick Fundas: Op-amp# 6" we have seen that the output of the Op-amp circuit oscillates between positive and negative saturation voltages when VIN is set to 0V. How the output voltage behave when the input voltage VIN is set (-2V) and when VIN is set (+2V)?

Ans:

Setting VIN (-2V) helps in the capacitor C2 to be charged to the negative threshold voltage faster. At the same time it takes more time for the capacitor C2 to be charged to the positive threshold. Hence the Op-amp output VOUT remains in positive saturation for more time than the time it remains in negative saturation. 

The opposite happens when VIN is set at (+2V). In that case, the Op-amp output VOUT remains in negative saturation for more time than the time it remains in positive saturation. 

Basically this is kind of a PWM (Pulse Width Modulation) circuit using an Op-amp. Pulse width modulation is achieved by varying VIN. In the picture below, the simulated waveform of the output VOUT is shown when VIN is varied from (-2V) to (+2V).

Figure 1: Pulse Width Modulation waveform (for circuit shown in Op-amp# 6)

Quick Fundas: Op-amp# 6

Let us see a little bit complex Op-amp circuit. Can you figure out how the Op-amp circuit shown below behaves when VIN (V2: DC voltage source) could be set anywhere between -2V to +2V? 

Figure1: Op-amp circuit# 6

Ans:

It might look tough, but it is not! :) Actually the circuit looks a bit clumsy. If you assume VIN is set to be zero, then you will find that the output of the Op-amp oscillating between +ve saturation voltage (around +10V) and -ve saturation voltage (around -10V). When the output of the Op-amp is at +ve saturation, the zener diode D1 (clamps @ 6.2V) and D2 (forward biased) sets +ve reference voltage (~7mV) at the non-inverting terminal of the Op-amp. As the capacitor C2 gets charged through R1, the voltage at the inverting terminal of the Op-amp increases and after time t1, just crosses the voltage present at the non-inverting input of the Op-amp. This turns the output to the -ve saturation voltage. The reference voltage at the non-inverting terminal gets changed to ~ (-7V). As the output turns -ve, the capacitor C2 gets charged through R1 to the -ve voltage. After time t2, the voltage at the inverting terminal of the Op-amp decreases just below the voltage set at the non-inverting terminal and the output of the Op-amp switches back to the +ve saturation voltage. The same continues. The output of the Op-amp remains at +ve saturation for the time t1 and remains at -ve saturation for the time t2. The time period of oscillation is (t1 + t2).
Simulated waveforms are shown below:

Figure 2: Simulated waveform of VOUT (VIN = 0V)

Figure 3: Simulated waveform of voltage at the input terminals of Op-amp (VIN = 0V)

Next: What happens when VIN is set at some voltage other than 0V?    

Quick Fundas: BJT# 1

What happens to VOUT when the source V1 is varied from +12V to +20V? Also, what will be the nature of variation of the current through R1 during this time? How could this circuit be useful? The Zener diode D2 has a breakdown voltage of 10V.

Figure 1: PNP Transistor Circuit

Hints: The circuit drives nearly constant current through R1 even though voltage V1 varies from +12V to +20V. Due to constant current through R1, voltage VOUT remains almost constant with respect to the positive rail (VOUT gets clamped with respect to positive rail of V1 irrespective of the variation of V1).

Using NPN transistors, the circuit below would provide nearly constant voltage ~9.6V at VOUT with respect to ground even if the input voltage varies between 12V and 30V.

Figure#2: NPN Transistor Clamp Circuit

One application of this circuit is to use this circuit to clamp the voltage of the gate drive of the MOSFET when the voltage used for the gate drive could vary over a wide range.   

Quick Fundas: Op-amp# 5

A slight improvement to the circuit described previously in "Quick Fundas: Op-amp# 4" is to add a capacitor C1 in parallel with R3. The capacitor C1 and R3 should be chosen appropriately to filter out over-voltage glitches that mostly occurs during power-up.

Figure 1: Improved Over-voltage detection circuit with latch

Quick Fundas: Op-amp# 4

Can we use the circuit similar to what is referred in "Quick Fundas: Op-amp# 3" to build an over-voltage monitoring circuit, which shall latch an over-voltage condition, i.e. even if the over-voltage occurs temporarily, the circuit should be able to continue driving the over-voltage shutdown trigger? The Op-amp should work with single +12V supply. The circuit should have provisions to adjust the threshold voltage levels for over-voltage detection (the voltage monitored could be different than the supply voltage to the Op-amp).

Ans:
There could be different ways to do it. The circuit below also should work. The circuit monitors the voltage "VMON" and drives "VOUT" to its positive rail when VMON goes above ~6.8V. The output VOUT gets latched even when VMON comes back to its nominal value. The latching feature is sometimes required for the user to understand an over-voltage condition has occurred. Changing R2, R3, R1 etc., the voltage threshold level could be adjusted. 

Figure 1: Over-voltage latch circuit diagram

The simulated waveforms are shown below:

Figure 2: Simulated waveform

     

Quick Fundas: Op-amp# 3

Another nice application of positive feedback to op-amp:

Can you think of building a SET-RESET latch circuit, which could be built using an op-amp, resistors and diodes? Assume that the op-amp is a rail-to-rail op-amp. 

Hints: You might need to use diodes in feedback and you might need to use positive feedback. 

If you are too much exhausted thinking, take look at the link below:

http://www.edn.com/design/other/4373768/Use-an-op-amp-as-a-set-reset-flip-flop

Quick Fundas: Op-amp#2

Another basic question that is sometimes asked to the fresh engineers during interviews:

When a positive feedback is added to an op-amp configured as comparably as shown in the picture below, how does the circuit behave? What is this circuit popularly known as? Could you please draw the transfer characteristics for the same?

In the picture below, VREF is a reference voltage, VIN is the voltage input and VOUT is the output of the Op-Amp.

Ans:

Without the positive feedback added using R2 above, the circuit behaves as a comparator. In that condition, considering the Op-Amp an ideal Op-Amp, when VIN rises just greater than VREF, the output of Op-Amp is driven to positive saturation voltage level VH. Again when VIN falls just lower than VREF, then VOUT goes to negative saturation voltage level VL. With R2 added as positive feedback, the circuit behaves as a Schmitt triggered comparator /buffer. With R2 in the circuit, when VIN rises more than VTH (see equation below) then VOUT is driven to positive saturation voltage level VH. Again when VIN falls lower than VTL (see equation below) then VOUT goes to negative saturation voltage level VL. Please note that VTH > VTL and the voltage difference (VTH - VTL) is the hysteresis band. The transfer characteristics is shown below:

VTH = VS - (R1/R2)*VL; 

VTL = VS - (R1/R2)*VH;

Where, VS = (1 + R1/R2)*VREF. 

    

Quick Fundas: Op-amp#1

There is a question that is commonly asked to the engineers appearing for the interviews at the initial stage of their career:

What are the few important parameters of an Op-amp? How do those parameters for a real-life Op-amp compare with those of a theoretically ideal Op-amp?

The table below shows some of the most important parameters of an ideal Op-amp vs. the same for a general purpose real-life Op-amp:

   

My Experience With "Noise": Part IVa

HIGH VOLTAGE SURGE:

In the previous parts the nature of ESD, EFT noise was discussed along with a brief illustration of the design techniques to make the electronics system more immune to the noise. I wish to present a much more detailed list of the circuit design and board layout recommendations and best practices later once we could touch upon all the types of the noises mentioned by the IEC/EN standards specifying noise immunity testing. In the subsequent few parts the threat of voltage surge and techniques will be discussed.

Before we go ahead to the next topic, I would like to put some food for thought through here. The question is related to EFT testing of Ethernet port. Have you ever seen shielded cable failing during EFT testing at a voltage level lower than the level at which the test passes with an unshielded cable? Can this happen? Please feel free to let your thought captured in the comments.

OK, coming back to the Voltage Surge topic, first we need to understand the nature of the surge. I consider voltage surge a bit different from the other types of electromagnetic disturbances such as ESD, EFT we have seen so far. I would not classify voltage surge as noise similar to ESD, EFT, RF as the frequency of surge is much lower compared to that of ESD, EFT etc. But the energy content in a surge pulse is much higher compared to ESD, EFT for a given voltage level. 

In the standard document IEC61000-4-5, the surge waveforms of open-circuit voltage and short circuit current are specified for a couple of different (front time/time to half-value) combinations, which closely simulate the real world surge waveforms, caused by overvoltage conditions from switching and lightning transients. If you are going for surge testing, you will need to go through the applicable standard documents to gather detailed information on the same. To present a basic idea here, I have illustrated the nature of the open-circuit voltage waveform of (1.2/50 us) surge voltage in the picture below:

Figure 1: Open-circuit voltage waveform (1.2/50 us) at the output of surge generator with no CDN connected

In Figure 1 above, T1 is the "Front Time", which is defined in the standard as a virtual parameter 1.67 times T (time taken by the impulse voltage to rise from 30% to 90% of its peak value).

T2 is the "time to half-value", which is the time interval between the virtual origin VO and the time instant when the impulse voltage falls to 50% of  its peak value.         

For the above voltage waveform, as specified in IEC61000-4-5 standard, 

T1 = 1.67 x T = 1.2 us +/- 30%

T2 = 50 us +/- 20%

In general, for a IO line or communication line, the peak value of the surge voltage applied during testing is 1KV. Compared to 1KV EFT pulses, we could easily make out that 1KV surge pulse would impose much more energy to the device under test.

In the next part we will see how the surge voltage is applied to the device under test and how we could handle that in the circuit design.

My Experience With "Noise": Part IIIc

As we have seen before, the EFT waveform specified in the IEC/EN standard document is intended to simulate the transients created by the interrupting inductive loads on the power mains, switching relays etc. Though primarily intended for injection on the product’s AC power cord, the EFT waveform can also be applied onto signal and control lines to simulate the coupling of the EFT onto these lines.

The EFT waveform specified in IEC 61000-4-4 has a rise time between 3.5 ns and 6.5 ns resulting, in a noise bandwidth (1/πtr) of approximately 90 MHz. Again, the EFT noise with frequencies upto (0.5/tr), i.e. 140MHz could also cause trouble. Hence let us consider the EFT noise with effective bandwidth upto 140 MHz could enter an electronic device or system through the cables connected to the ports. We need to design the filter circuit accordingly.

Mainly two types of ports are distinguished by the standard EN/IEC 61000-4-4: power ports and signal ports. A signal port could be an IO port, sensor input port or any communication port such as Ethernet, USB, serial etc. In general the common tactics to deal with EFT noise and similar are:

1. Avert:
Implement a circuit which can resist the noise at the port entry so that the noise to the extent enough to upset the device, doesn't enter through the ports. Using a common-mode choke at the power entry or on communication channels carrying differential signals at the port is one good example.

2. Divert:
Implement a circuit which can bypass the noise to a good ground connection (such as chassis ground). Implementing port filter or using EFT protection devices such as TVS diodes, capacitors are good examples of this method. TVS devices are used to divert the transient current, clamp the voltage and keep the internal circuitry safe.

Most of the time, a combination of both the above is desirable to be implemented in the design. As shown below, the TVS diode D1, capacitors CL1, CH1 and the Common Mode Choke forms the circuit which filters the noise at the port entry and prevents the noise (Averts) to reach the device. After the Common Mode Choke on the device-side, there are two decoupling capacitors CL2 and CH2 shown which divert the noise to the ground and prevents it further from entering to the device. Please note that the circuit below can handle common-mode noise only. Usually EFT noise is Common Mode in nature, but there should be some provision kept to handle Differential Mode noise also (not shown below).    

The red arrow mark in the picture below shows that the noise gets weaker at each stage of the filter/protection circuit. The strength of the noise entering the device gets weaker enough not to upset its functionality. Please note that the ground path needs to be very good to provide a strong & solid return path for the noise.

 

I plan to mention some of the board layout level techniques after we discuss all other EMC tests. In the next part, we will venture into high energy voltage surge.

 

     

My Experience With "Noise": Part IIIb

EFT: Understanding Test Methodologies To Avoid Failures

In the previous post, the source of EFT noise is presented in brief. The idea behind this article is to provide a highlight of this topic and hence I'm not going into depth. But we need to know a bit more on the EFT test wave characteristics and the test methodology that is described in IEC 61000-4-4. That might help in understanding what kind of noise might get into the system during testing if proper precautionary measures are not implemented in the design. The waveform below shows the EFT test waveform as suggested in the standard.

EFT Waveform Per Standard IEC 61000-4-4

The "Repetition Period" above depends on the frequency selected. As recommended in the latest standard, the pulse repetition period could be 5KHz (as it was prescribed in earlier versions) or 100KHz (suggested as more similar to practical, but not mandatory). Hence the repetition period could be 200us (for 5KHz) or 10us (for 100KHz). The "Burst Duration" above is the time duration for 75 pulses, i.e. the burst duration is 15ms when the pulse repetition frequency is selected as 5KHz. Please note that, irrespective of the pulse repetition frequency selected as either 5KHz or 100KHz, the energy imparted by the EFT pulses remain same for both of these cases.

The peak voltage level of the EFT noise pulses could be selected as it is recommended in the product specific standards for the specific channel type (power/IO/Communication) for the specific equipment under test (EUT). For example the peak test voltage levels could be +/-2KV for AC power lines and +/-1KV for other lines (DC power/signal/communication etc). The EFT noise needs to be applied to the EUT for 1 second for each polarity of the peak voltage level tested. 

  

The link below could serve as a quick reference to the waveforms, spectral characteristics, equations and test methodology etc.

http://www.teseq.com/com/en/service_support/technical_information/4_Transient_immunity_testing.pdf 

Next we will discuss more on the design measures to avoid failures due to EFT noise. 

My Experience With "Noise": Part IIIa

Electrical Fast Transient (EFT):

Anybody having experience with EMC testing should be well conversant with this term "EFT". For others, EFT is also a transient noise, that occurs due to the switching of power relays or the interruption of inductive loads on the power mains. The standard IEC 61000-4-4 or EN61000-4-4 describes the test procedures for subjecting EFT noise to the equipment under test, trying to simulate the real life EFT noise that might be present in an industrial environment. While designing an electronic device or system, the designer must take precautions against the design's vulnerability to EFT. As I have experienced, things gets much harder to fix a circuit failing in EFT test if the appropriate measures had not been incorporated in the design proactively.

Understanding the source of EFT:

When an electrical circuit is switched off, the current flowing through the switch contacts is interrupted more or less instantaneously. Hence at the moment of switching there is a high (ideally infinite) di/dt. Due to stray inductance associated with the wiring, types of inductive loads such as motors or solenoids, the voltage developed across an inductance L by a changing current i is:

V = - L . di/dt

This high instantaneous voltage causes the increasing air gap across the contacts to break down and a current flows again, which collapses the voltage spike, so that the briefly formed arc extinguishes. But this re-interrupts the current, hence another voltage spike appears, creating a further arc. This process repeats itself until the air gap is large enough to sustain the applied voltage without breakdown. At this point the circuit can be said to be properly switched off. The visible effect of this is a brief spark between the breaking contacts of the switch, but actually this consists of a series of microsparks whose repetition rate and amplitude depend on the circuit and switch parameters.

This burst of noise is the EFT noise which can appear at the power mains inlet of the device. Since the pulses are very fast (order of nanoseconds) they couple effectively through mutual capacitance and inductance to other wiring in close proximity to the source wiring such as control, communication or sensor lines. Voltage spikes typically of hundreds or thousands of volts, may appear on any such coupled circuits. 

When we should worry about:

Though it is not impossible for the transients to be coupled into a victim in close proximity inductively, but generally EFT noise enters the product via the cable connections, getting coupled capacitively. Any electronic device with power cable(s), IO cable(s) or communication cable(s) is the candidates susceptible to failure due EFT noise if the proper design methodologies are not followed to prevent failure due to EFT. On signal ports the EFT spikes are almost invariably in common mode. Common mode coupling on mains includes the protective earth wire.

In the next part (IIIb) we will discuss more on the measures to avoid the design getting susceptible to failures due to EFT noise.