My Experience With "Noise": Part Vb

CONDUCTED RF: Effects of RF Interference on electronic components (Work in progress)

It would be good to understand how RFI (Radio Frequency Interference) affects the functionality of the different electronic components. I saw a nice article "Integrated Circuit Susceptibility to Conducted RF Interference", published in the Compliance Engineering magazine, which describes the effect of RFI on the functionality of different active electronic components such as diode, BJT, MOS transistor, Op-amp, Digital IC individually. The link is given below:

http://www.ce-mag.com/archive/2000/novdec/fiori.html

This could serve as a good starting point for understanding and predicting what kinds of components are there at the board entry (generally IO circuit, power circuit, communication ports) which could see the RF noise. Once it could be predicted the behavior of the components in the circuit with RF Interference, necessary precautions could be taken to prevent the failures.  

  

My Experience With "Noise": Part Va

CONDUCTED RF:

Conducted RF immunity test is performed to check whether the EUT functionality is compromised or not, when a RF noise gets coupled to the EUT through its one or more ports. Some how I have not seen major issues with this test and that might be because I have worked more on digital circuits. There might be exceptions, but in general, digital circuits are less susceptible to continuous RF while analog circuits are more so.

The purpose of the test is to simulate the proximity of the EUT and its connected cables to radio transmitters and RF manufacturing equipment operating at low frequencies. These frequencies are not easy to test as it is hard to generate uniform fields in typical test facilities at frequencies much below 80MHz, but for typical sizes of apparatus the immunity problems at frequencies below 80MHz are normally associated with cable coupling, so conducted testing of the cables is seen as a reasonable alternative to radiated methods at such frequencies. Conducted RF immunity testing is also a lot less costly to do properly than radiated RF immunity. Please refer the link below and the IEC 61000-4-6 standard to learn about the conducted RF test procedures

http://www.compliance-club.com/archive/old_archive/011021.htm

The standard cable-coupled RF immunity test of IEC 61000-4-6 specifies an injected level, typically of 3V or 10V open circuit voltage from a source impedance of 150 ohm, in common mode into each interface to be tested. The test frequency range is 150kHz – 80MHz (expandable up to 230MHz). So, there are two principal parameters defined in conducted RF tests, the frequency range and the test level.

The exact frequency range used for a test is defined in the corresponding product standards. Frequency range is chosen defending on the size of cable and EUT. In general, if the cable and EUT length is λ/4, the upper frequency may be increased. This rule also holds true for the start frequency which may be higher than the specified 150 kHz. Start frequencies would be increased when the cable and EUT length is λ/4.

My Experience With "Noise": Part IVd

We were discussing about surge voltage transient and how to make our designs more and more immune to this kind of disturbances...we are not done yet.

The picture below shows a circuit how a TVS doide is connected one one input port, which shows the parasitic inductors L1, L2, L5 & L6 seen by the physical copper traces on the board when a high frequency transient V1 is applied to the input. Please note that the equivalent load at the input port is represented by a capacitor and resistor in parallel: C1 & R1. Also note that the signal ground and frame ground are usually separate and usually connected together by a capacitor (usually having high voltage rating such as 2KV) and high value resistance (~10M ohm); that is what is represented by C2 and R2 in the Figure 1 below. Please note that V1 represents a surge transient source and that is why it is referenced to "FRAME GND" not the signal ground. Also it is to be noted that the TVS device (represented by D1 in Figure 1) or any other suitable transient suppressor device shall always be connected between the line it intends to protect and always the "FRAME GND" not the signal ground (assuming these two ground connections are not the same). 

Figure 1: Surge suppressor & parasitic inductance

Each piece of copper trace on the PCB imposes some inductance to a "high frequency" transient current, caused by ESD, EFT or Surge. Since the objective of the transient suppressing device D1 here is to divert the transient energy back to the source from right at the port entry, the protection device shall ideally placed right between the port connector pins: signal under protection and frame ground. But it is not always practically possible to do the same. So care must be taken to make the traces to TVS as short and wide as possible. The intention here is to reduce the values of the parasitic inductors L1, L5 and L6 to "practical" zeros. The trace represented by L2 could have a longer length and theoretically it should be better to have a bit of inductance on that trace (L2) to offer impedance to any transient noise tries to propagate on its path to the device under protection (but if it is permitted for its correct functioning).

We will discuss this further when we will take a look at the some layout design techniques. Next topic I would like to pick would be "conducted RF".    

EMC: Theories, Equations, Foundation

I am going to add the following link to the blog page, which contains many useful information for engineers like me who has lost a touch with the academics; I found the tutorials very helpful in refreshing our knowledge on the foundation, based on which we take some of our engineering design decisions:

http://www.learnemc.com/EMC-Tutorials.html    

My Experience With "Noise": Part IVc

I beg your pardon to all who were following this blog, for an extremely long silence on this page. Actually I got caught in an EMC mess starting from the beginning of this year and got occupied for last few months. The problem was radiated emission related and it helped me gathering some more knowledge around that topic and we will discuss something similar when we discuss on "radiated emission". 
But I can't help sharing a lesson I learned from my experience: "I would always run Radiated Emission (RE) Test FIRST after I could power a prototype successfully, before running all other EMC immunity tests, if I feel there is a risk with RE. So that I could fix any issues related to RE first". We will discuss on this later, but let us just continue on what we were discussing.
In the previous part we have seen how the surge testing gets conducted as per IEC 61000-4-5 on the un-shielded IO lines. There are again different test procedures specified in that standard for the EUT having balanced unshielded IO/communication lines, shielded IO, communication line etc. I am not going through all of those test procedures and would recommend you to get hands on the standards and be thorough with the test procedures to be well equipped with the knowledge rather than learning in the hard way while going through the testing.     

So far, do we understand the difference between the EFT and Surge? I found the the article in the link below, which is very useful to understand that difference between EFT & Surge:
http://7ms.com/enr/online/2007/01_02/notebook.html

Just to highlight a few important takeaways from the article, please note that the rise time of the surge voltage is approximately 1.2us, where as the rise time of the EFT waveform is ~5ns.
Now, given the rise time of a pulse = tr, the knee frequency Fknee is given by the following equation:
Fknee = 1/(pi*tr);
For surge voltage having rise time of 1.2us, Fknee = 265KHz, approximately 300KHz;
Where as on the other hand, EFT voltage having rise time of 5ns, Fknee = 63.7MHz, approximately 65MHz; Hence, surge is a high energy, low frequency transient and EFT is a low energy high frequency transient.
The following picture shows comparison of energy level produced by different types of electrical transients such as EFT, ESD, surge, ring wave (we will discuss next) etc, having same peak voltage level. Note that the energy contained in surge voltage transient is the highest among all:

The measures for making the design tolerant to the required level of surge voltage is quite the same as the techniques used to make the design immune to ESD transients and EFT:
(1) Use transient suppressors or "SHIELD" to "divert" the voltage transient to the "Frame ground" or "Chassis ground" with MINIMUM RESISTANCE AND INDUCTANCE (ideally zero) on the return path. The following table shows a comparison of different types of transient suppression devices to be used to divert the energy to the frame/chassis ground. Please note that the transient suppression devices used for diverting the "surge transients" shall be required to handle maximum amount of energy compared to other transients. But it need not to be as fast as that required for EFT or ESD.

Table 1: Comparison of different transient protection devices

(2) Implement appropriate filtering for the transient noise due to voltage surge to get filtered out so that the disturbance does not affect the functionality of the design or damage the devices while operating. For filtering power lines, bandwidth is not an issue. In principal, we could use enough filtering to control both surge and EFT. Audio frequency signal lines can usually be filtered adequately as well. Surge, having a bandwidth of 300kHz, requires a filter cut-off of 30kHz or less in order to provide sufficient protection. Where as EFT, having a bandwidth of 60MHz, would need a cutoff of 6MHz or less, might be acceptable for many RS 232 lines, but too low for many digital data streams.

In the next part I am going to discuss some more on the design tips for surge protection. 

My Experience With "Noise": Part IVb

HIGH VOLTAGE SURGE: TESTING 

In the previous chapter IVa, the nature of the surge voltage waveform as described in the  standard IEC/EN 61000-4-5 was illustrated. 

The coupling of surge waveforms into a system under test has many variations and a full description might not be possible here as I plan to keep it simple at this stage. I plan to describe specific cases some point of time later where I will include a much more detailed description. 

There are general concepts that will be discussed here. In practice all testing is done based on a specific test standard and the standards give detailed descriptions as I am referring to IEC/EN 61000-4-5 standard.

Surges can be applied to both power and data lines. The considerations are similar. The test setup must be able to deliver the stress to the system under test without interfering with system operation before and after the application of the stress. The test setup must also prevent damage or upset to electronics needed to exercise the system under test. This is done with a combination of a coupling network to apply the stress to the system under test and decoupling network to prevent damage or upset to auxiliary equipment. This "Coupling & Decoupling Network" is a commonly known by the short form "CDN". An example is shown in Figure 1 for stressing a set of data lines. The network in Figure 1 allows the stressing of any of the data lines with respect to any of the other data lines or ground. The parallel combination of the capacitor and the surge arrestor feeds the stress into the system. In most cases the arrestor is not included and the surge is coupled into the system capacitively. High speed data lines may not be able to tolerate the micro Farad sized capacitors needed for coupling. An arrestor, such as a gas tube, provides a low capacitive alternative.

Figure 1: Typical Surge Voltage Set-up on IO ports

Test setups for stress to power supply lines are similar. The values of the coupling capacitor may be larger and it is unlikely that the capacitance will be too large so that the use of arrestors for coupling is not needed. Resistors would not usually be used in the decoupling network and capacitive filters may be added between lines on the opposite side of the decoupling network from the unit under test. 

The test set-up described above is necessary to understand how surge voltage disturbances are applied to system/equipment under test and might make it easier to understand how to protect the equipment against such disturbances. In the next post we will see some examples of design practices for surge protection.